The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Dec. 04, 2002
Applicants:
Pavel Klinger, San Jose, CA (US);
Sreeni Maheshwarla, Sunnyvale, CA (US);
Inventors:
Pavel Klinger, San Jose, CA (US);
Sreeni Maheshwarla, Sunnyvale, CA (US);
Assignee:
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8247 ;
U.S. Cl.
CPC ...
Abstract
A method of forming an electrically erasable non-volatile memory cell array. Each memory cell includes a floating gate, a block of insulation material over the floating gate, and a control gate disposed laterally adjacent to and over the floating gate. The insulation material block is formed with a planarized upper surface (using a dummy poly layer as a planarization etch stop). The control gate is formed with a planarized upper surface (using the insulation material block upper surface as a planarization etch stop).