The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2005
Filed:
Aug. 02, 2001
Sean Boylan, Rahoon, IE;
Derek Coburn, Dundalk, IE;
Tadhg Creedon, Furbo, IE;
Denise DE Paor, Carraroe, IE;
Vincent Gavin, Galway, IE;
Kevin J Hyland, Dublin, IE;
Suzanne M Hughes, Galway, IE;
Kevin Jennings, Ballinasloe, IE;
Mike Lardner, Tuam, IE;
Brendan Walsh, Galway, IE;
Sean Boylan, Rahoon, IE;
Derek Coburn, Dundalk, IE;
Tadhg Creedon, Furbo, IE;
Denise De Paor, Carraroe, IE;
Vincent Gavin, Galway, IE;
Kevin J Hyland, Dublin, IE;
Suzanne M Hughes, Galway, IE;
Kevin Jennings, Ballinasloe, IE;
Mike Lardner, Tuam, IE;
Brendan Walsh, Galway, IE;
3Com Corporation, Santa Clara, CA (US);
Abstract
A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be 'off-chip'. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.