The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2005

Filed:

Dec. 22, 2000
Applicants:

Ananda Sarangi, Beaverton, OR (US);

Rachael Jade Parker, Forest Grove, OR (US);

Edward P. Osburn, Folsom, CA (US);

Gregory F. Taylor, Portland, OR (US);

Inventors:

Ananda Sarangi, Beaverton, OR (US);

Rachael Jade Parker, Forest Grove, OR (US);

Edward P. Osburn, Folsom, CA (US);

Gregory F. Taylor, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F001/24 ; G06F001/32 ;
U.S. Cl.
CPC ...
Abstract

A dynamic processor configuration and power-up programs a processor's fuse block with configuration signals during processor manufacturing. The processor configuration signals include a core voltage identifier and a system bus frequency identifier. When power is applied to the platform, a control signal is used to prevent power-up of the platform's processor related circuitry. While the platform awaits full power-up, the fuse block is powered up. When the fuse block is powered up, the control signal is used to allow the configuration signals to be read from the fuse block. The processor is configured with core voltage and system bus frequency based on the values read from the fuse block. The platform then performs its boot-up sequence.


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