The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2005
Filed:
Feb. 22, 2002
Ashish Gupta, San Jose, CA (US);
William R. Bryg, Saratoga, CA (US);
Ashish Gupta, San Jose, CA (US);
William R. Bryg, Saratoga, CA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
A method of accessing a plurality of memories in an interleaved manner using a contiguous logical address space includes providing at least one map table. The at least one map table includes a plurality of entries. Each entry includes a plurality of entry items. Each entry item identifies one of the memories. A first logical address is received. The first logical address includes a plurality of address bits. The plurality of address bits includes a first set of address bits corresponding to a first set of entries in the at least one map table. A first entry in the first set of entries is identified based on the first set and a second set of the address bits. A first entry item in the first entry is identified based on a third set of the address bits. The memory identified by the first entry item is accessed.