The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2005

Filed:

Sep. 19, 2002
Applicants:

Brian W. Amick, Austin, TX (US);

Lynn Warriner, Round Rock, TX (US);

Claude R. Gauthier, Cupertino, CA (US);

Tri Tran, San Leandro, CA (US);

Inventors:

Brian W. Amick, Austin, TX (US);

Lynn Warriner, Round Rock, TX (US);

Claude R. Gauthier, Cupertino, CA (US);

Tri Tran, San Leandro, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H003/20 ;
U.S. Cl.
CPC ...
Abstract

A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a 'virtual' ground reference voltage is provided. The 'virtual' ground voltage reference, being greater than a zero volt ground voltage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ ground reference voltage off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.


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