The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2005
Filed:
Aug. 09, 2002
Ashok Prabhu, San Jose, CA (US);
Shaw Wei Lee, Cupertino, CA (US);
Ashok Prabhu, San Jose, CA (US);
Shaw Wei Lee, Cupertino, CA (US);
Eastman Kodak Company, Rochester, NY (US);
Abstract
An apparatus and method for wafer level packaging of optical imaging die using conventional semiconductor packaging techniques. The method comprises forming spacing structures over imaging circuitry on a plurality of dice on a semiconductor wafer, attaching a transparent template on the spacing structures on the plurality dice on the semiconductor wafer, singulating the plurality of dice on the semiconductor wafer, and packaging the plurality of dice after being singulated from the wafer. The apparatus comprises a semiconductor wafer including a plurality of dice, each of the dice including imaging circuitry and bond pads. A translucent template is positioned over the semiconductor wafer. The translucent plate includes die cover regions configured to cover the imaging circuitry of the dice and recess regions to exposed the bond pads of the dice respectively. The resulting chip, after further packaging steps, includes the substrate, the semiconductor die having imaging circuitry and bond pads, the semiconductor die mounted onto the substrate and the transparent template positioned over the semiconductor die. The transparent template includes the a die cover region configured to be positioned over the imaging circuitry of the semiconductor die and recess regions to expose the bond pads of the semiconductor die.