The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Dec. 02, 2003
Masashi Horiguchi, Kawasaki, JP;
Masayuki Nakamura, Ome, JP;
Sadayuki Ohkuma, Hidaka, JP;
Kazuhiko Kajigaya, Iruma, JP;
Yoshinobu Nakagome, Hamura, JP;
Masashi Horiguchi, Kawasaki, JP;
Masayuki Nakamura, Ome, JP;
Sadayuki Ohkuma, Hidaka, JP;
Kazuhiko Kajigaya, Iruma, JP;
Yoshinobu Nakagome, Hamura, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.