The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6870771 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 22, 2005

Filed:

Jul. 24, 2002
Applicants:

Mitsuhiro Tomoeda, Hyogo, JP;

Atsushi Ohba, Hyogo, JP;

Toshimasa Makino, Hyogo, JP;

Inventors:

Mitsuhiro Tomoeda, Hyogo, JP;

Atsushi Ohba, Hyogo, JP;

Toshimasa Makino, Hyogo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C016/06 ;
U.S. Cl.
CPC ...
Abstract

In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.


Find Patent Forward Citations

Tomoeda, Mitsuhiro. (2005). Nonvolatile semiconductor memory device that can suppress effect of threshold voltage variation of memory cell transistor (U.S. Patent No. 6870771). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6870771

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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