The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Oct. 03, 2003
Yan Chong, Stanford, CA (US);
Chiakang Sung, Milpitas, CA (US);
Bonnie Wang, Cupertino, CA (US);
Khai Nguyen, San Jose, CA (US);
Joseph Huang, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Philip Pan, Freemont, CA (US);
IN Whan Kim, San Jose, CA (US);
Gopi Rangan, Santa Clara, CA (US);
Tzung-chin Chang, San Jose, CA (US);
Surgey Y. Shumarayev, San Leandro, CA (US);
Thomas H. White, Santa Clara, CA (US);
Yan Chong, Stanford, CA (US);
Chiakang Sung, Milpitas, CA (US);
Bonnie Wang, Cupertino, CA (US);
Khai Nguyen, San Jose, CA (US);
Joseph Huang, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
Philip Pan, Freemont, CA (US);
In Whan Kim, San Jose, CA (US);
Gopi Rangan, Santa Clara, CA (US);
Tzung-Chin Chang, San Jose, CA (US);
Surgey Y. Shumarayev, San Leandro, CA (US);
Thomas H. White, Santa Clara, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.