The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Mar. 18, 2003
John A. Schadt, Bethlehem, PA (US);
William B. Andrews, Emmaus, PA (US);
Zheng Chen, Macungie, PA (US);
Anthony K. Myers, Hamburg, PA (US);
David A. Rhein, Reading, PA (US);
Warren L. Ziegenfus, Emmaus, PA (US);
Fulong Zhang, Willow Grove, PA (US);
Ming Hui Ding, Allentown, PA (US);
Larry R. Fenstermaker, Nazareth, PA (US);
John A. Schadt, Bethlehem, PA (US);
William B. Andrews, Emmaus, PA (US);
Zheng Chen, Macungie, PA (US);
Anthony K. Myers, Hamburg, PA (US);
David A. Rhein, Reading, PA (US);
Warren L. Ziegenfus, Emmaus, PA (US);
Fulong Zhang, Willow Grove, PA (US);
Ming Hui Ding, Allentown, PA (US);
Larry R. Fenstermaker, Nazareth, PA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A programmable logic device (PLD) with a programmable logic core, block memory, and I/O circuitry has one or more blocks of standard-cell logic (SLBs) that are integrated into the PLD design to enable each SLB to be programmably connected to any one or more of the programmable core, the block memory, and/or the I/O circuitry. The addition of standard-cell-based functional blocks creates a PLD with increased overall logic density, a net smaller die size per function, lowered cost, and improvements to both power and performance characteristics relative to equivalent conventional PLDs, such as FPGAs.