The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
May. 16, 2002
Applicant:
Bradley A. Sharpe-geisler, San Jose, CA (US);
Inventor:
Bradley A. Sharpe-Geisler, San Jose, CA (US);
Assignee:
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F007/38 ;
U.S. Cl.
CPC ...
Abstract
An input/output buffer is provided which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a first pair of CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. Switching circuitry includes transistors which drive gates of the CMOS transistors to set the output (OUT) with a current level and a voltage level depending on a desired output drive current and voltage.