The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2005
Filed:
Feb. 14, 2003
Ercan Adem, Sunnyvale, CA (US);
John E. Sanchez, Palo Alto, CA (US);
Darrell M. Erb, Los Altos, CA (US);
Suzette K. Pangrle, Cupertino, CA (US);
Ercan Adem, Sunnyvale, CA (US);
John E. Sanchez, Palo Alto, CA (US);
Darrell M. Erb, Los Altos, CA (US);
Suzette K. Pangrle, Cupertino, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.