The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2005
Filed:
Dec. 06, 2000
Kazuo Kubo, Tokyo, JP;
Hideo Yoshida, Tokyo, JP;
Hiroshi Ichibangase, Tokyo, JP;
Hidenori Taga, Tokyo, JP;
Eiichi Shibano, Tokyo, JP;
Tadami Yasuda, Tokyo, JP;
Kazuo Kubo, Tokyo, JP;
Hideo Yoshida, Tokyo, JP;
Hiroshi Ichibangase, Tokyo, JP;
Hidenori Taga, Tokyo, JP;
Eiichi Shibano, Tokyo, JP;
Tadami Yasuda, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
KDD Submarine Cable Systems Inc., Tokyo, JP;
Abstract
In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit, a first error correction code is generated by an RS (239, 223) coding circuit, the order is returned to the original order by a first deinterleaving circuit, and a second error correction code is generated by an RS (255, 239) coding means. The second error correction code is decoded by an RS (255, 239) decoding circuitto correct errors in the information, the order of information is changed by a second interleaving circuit, the first error correction code is decoded by an RS (239, 223) decoding circuitto correct residual errors in the information, and the order is returned to the original order by a second deinterleaving circuit