The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2005
Filed:
Dec. 19, 2002
Henry L. Edwards, Garland, TX (US);
Sameer Pendharkar, Richardson, TX (US);
Joe Trogolo, Plano, TX (US);
Tathagata Chatterjee, Allen, TX (US);
Taylor Efland, Dallas, TX (US);
Henry L. Edwards, Garland, TX (US);
Sameer Pendharkar, Richardson, TX (US);
Joe Trogolo, Plano, TX (US);
Tathagata Chatterjee, Allen, TX (US);
Taylor Efland, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (), and an oxide region () overlapping the moat region. A double-diffusion region () is formed within the oxide region, having end cap regions () that are effectively deactivated utilizing geometric and implant manipulations.