The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2005

Filed:

May. 27, 2004
Applicants:

Sung-il Cho, Seoul, KR;

Seung-young Son, Yongin-si, KR;

Chang-jin Kang, Suwon-si, KR;

Kyeong-koo Chi, Seoul, KR;

Ji-chul Shin, Seongnam-si, KR;

Inventors:

Sung-IL Cho, Seoul, KR;

Seung-Young Son, Yongin-si, KR;

Chang-Jin Kang, Suwon-si, KR;

Kyeong-Koo Chi, Seoul, KR;

Ji-Chul Shin, Seongnam-si, KR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/8242 ;
U.S. Cl.
CPC ...
Abstract

Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.


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