Multi-stage interconnect architecture for complex programmable logic devices

Abstract

Systems and methods are disclosed for providing a multi-stage interconnect architecture, such as for high density and high performance complex programmable logic devices. As an example, a first stage of a two-stage interconnect architecture programmably routes signals from a global routing structure to a second stage of the two-stage interconnect architecture. The second stage routes signals from the first stage to a number of logic blocks. The second stage also-optionally routes feedback signals from the logic blocks along with signals from associated I/O terminals back to the logic blocks to provide local feedback capability.