The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2005
Filed:
Sep. 17, 2003
Hitoshi Asada, Kawasaki, JP;
Hiroaki Inoue, Kawasaki, JP;
Hitoshi Asada, Kawasaki, JP;
Hiroaki Inoue, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
The semiconductor device comprises a gate electrodeformed on a semiconductor substrate, a source regionhaving a lightly doped source regionand a heavily doped source region, a drain regionhaving a lightly doped drain regionand a heavily doped drain region, a first silicide layerformed on the source region, a second silicide layerformed on the drain region, a first conductor plugconnected to the first silcide layer and a second conductor plugconnected to the second silicide layer. The heavily doped drain region is formed in the region of the lightly doped region except the peripheral region, and the second silicide layer is formed in the region of the heavily doped drain region except the peripheral region. Thus, the concentration of the electric fields on the drain region can be mitigated when voltages are applied to the drain region. Thus, even with the silicide layer formed on the source/drain region, sufficiently high withstand voltages of the high withstand voltage transistor can be ensured. Furthermore, the drain region alone has the above-described structure, whereby the increase of the source-drain electric resistance can be prevented while high withstand voltages can be ensured.