Array of floating gate memory cells having strap regions and a peripheral logic device region

Abstract

A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate having a plurality of spaced apart isolation regions and active regions on the substrate substantially parallel to one another in the column direction, and an apparatus formed thereby. Floating gates are formed in each of the active regions. In the row direction, trenches are formed that are filled with a conducting material such as metal or metalized polysilicon to form blocks of the conducting material that constitute source lines. Each source line extends over and is electrically connected to one of the source regions in each of the active regions.