The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2005
Filed:
Jul. 30, 2003
Jane Xin-leblanc, Santa Clara, CA (US);
Wai Lau, Taikoo Shing, HK;
Jane Xin-LeBlanc, Santa Clara, CA (US);
Wai Lau, Taikoo Shing, HK;
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A pull-down circuit for pulling a high-impedance node to ground when a pull-down (PD) signal driving the pull-down circuit is Logic 1. The pull-down circuit comprises: 1) a first pull-down N-channel transistor having a drain coupled to the high-impedance node, a gate coupled to the PD signal, and a source coupled to a common node; 2) a second pull-down N-channel transistor having a drain coupled to the common node, a gate coupled to the PD signal, and a source coupled to a ground rail;, wherein the first and second pull-down N-channel transistors are off when the PD signal is Logic 0 and are on when the PD signal is Logic 1; and 3) a gate-biasing circuit driven by the PD signal. The gate-biasing circuit is off when the PD signal is Logic 1 and the gate-biasing circuit applies a Logic 1 bias voltage to the common node when the PD signal is Logic 0. The Logic 1 bias voltage creates a negative Vgs bias on the first pull-down N-channel transistor when the PD signal is Logic 0. An analogous pull-up circuit also is disclosed.