The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2005
Filed:
Jun. 04, 2001
Applicant:
Akiyoshi Yamamoto, Tokyo, JP;
Inventor:
Akiyoshi Yamamoto, Tokyo, JP;
Assignee:
Elpida Memory, Inc., Tokyo, JP;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/0175 ;
U.S. Cl.
CPC ...
Abstract
A semiconductor apparatus including programmability that may allow a SSTL interface or LVTTL interface is provided. A reference configuration circuit () may provide a primary reference potential VREFand secondary reference potential VREF. Reference configuration circuit () may include a bond pad (PAD), a reference potential generation circuit (), a control circuit (), a reference selection circuit (), and a secondary reference potential generation circuit (). During a wafer test mode, primary reference potential VREFand secondary reference potential VREF may be provided from a potential that may be applied to bond pad (PAD).