The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2005

Filed:

Nov. 27, 2002
Applicants:

Roy E. Scheuerlein, Cupertino, CA (US);

Matthew P. Crowley, San Jose, CA (US);

Inventors:

Roy E. Scheuerlein, Cupertino, CA (US);

Matthew P. Crowley, San Jose, CA (US);

Assignee:

Matrix Semiconductor, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C008/00 ;
U.S. Cl.
CPC ...
Abstract

A memory array decoder organization readily interfaces to array lines having extremely dense pitch, and in particular interfaces to extremely dense array lines of a three-dimensional memory array. In an exemplary embodiment, a multi-headed decoder includes a group of array line driver circuits associated with a single decode node. Each array line driver circuit couples its associated array line through a first device to an associated upper bias node which is generated to convey either a selected bias condition or an unselected bias condition thereon appropriate for the array line. Each array line driver circuit also couples its associated array line through a second device to an associated lower bias node which is generated to convey an unselected bias condition appropriate for the array line. The array line driver circuits for several different decode nodes may be physically arranged in one or more banks.


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