The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2005
Filed:
Jun. 19, 2003
H. Bernhard Pogge, Hopewell Junction, NY (US);
Roy Yu, Poughkeepsie, NY (US);
Chandrika Prasad, Wappingers Falls, NY (US);
Chandrasekhar Narayan, Hopewell Junction, NY (US);
H. Bernhard Pogge, Hopewell Junction, NY (US);
Roy Yu, Poughkeepsie, NY (US);
Chandrika Prasad, Wappingers Falls, NY (US);
Chandrasekhar Narayan, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.