The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2005
Filed:
Jun. 11, 2002
Hideomi Koinuma, Tokyo, JP;
Masashi Kawasaki, Sagamihara, JP;
Toyohiro Chikyow, Tsukuba, JP;
Yoshiyuki Yonezawa, Yokosuka, JP;
Yoshinori Konishi, Yokosuka, JP;
Hideomi Koinuma, Tokyo, JP;
Masashi Kawasaki, Sagamihara, JP;
Toyohiro Chikyow, Tsukuba, JP;
Yoshiyuki Yonezawa, Yokosuka, JP;
Yoshinori Konishi, Yokosuka, JP;
National Institute for Materials Science, Ibaraki, JP;
Tokyo Institute of Technology, Tokyo, JP;
Fuji Electric Corporate Research and Development, Kanagawa, JP;
Abstract
A composite integrated circuit is characterized in that to put an oxide thin film into practical use as an electronic device, a highly crystalline oxide thin film is grown on a silicon substrate. A MOS circuit and a thin film capacitor are formed independently, and the two substrates are laminated using an epoxy resin. They are connected through buried wiring, thereby constituting a composite circuit package. As a second substrate, a (110) plane orientation silicon substrate is used which differs from the IC substrate with a (100) plane. On the (110) silicon substrate after the termination processing, a dielectric layer is film deposited, followed by forming an upper electrode, and by forming a thin film coil. Insulating magnetic gel is filled between coil wires and its upper portion. Thus, the fabrication process of the thin film coil and the composite integrated circuit is completed.