The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 2005
Filed:
Dec. 15, 2003
Michael Hübner, Schönau, DE;
Gunnar Krause, München, DE;
Justus Kuhn, München, DE;
Jochen Müller, München, DE;
Peter P{hacek Over (O)}chmüller, Colchester, VT (US);
Jürgen Weidenhöfer, München, DE;
Michael Hübner, Schönau, DE;
Gunnar Krause, München, DE;
Justus Kuhn, München, DE;
Jochen Müller, München, DE;
Peter P{hacek over (o)}chmüller, Colchester, VT (US);
Jürgen Weidenhöfer, München, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.