The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2005
Filed:
Sep. 28, 2000
Rajendran Nair, Hillsboro, OR (US);
Siva G. Narendra, Beaverton, OR (US);
Tanay Karnik, Portland, OR (US);
Vivek K. DE, Beaverton, OR (US);
Rajendran Nair, Hillsboro, OR (US);
Siva G. Narendra, Beaverton, OR (US);
Tanay Karnik, Portland, OR (US);
Vivek K. De, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus for providing a weak inversion mode metal-oxide-semiconductor (MOS) decoupling capacitor is described. In one embodiment, an enhancement-mode p-channel MOS (PMOS) transistor is constructed with a gate material whose work function differs from that commonly used. In one exemplary embodiment, platinum silicate (PtSi) is used. In alternate embodiments, the threshold voltage of the PMOS transistor may be changed by modifying the dopant levels of the substrate. In either embodiment the flat band magnitude of the transistor is shifted by the change in materials used to construct the transistor. When such a transistor is connected with the gate lead connected to the positive supply voltage and the other leads connected to the negative (ground) supply voltage, an improved decoupling capacitor results.