The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 2005
Filed:
Oct. 26, 1999
Chau Chin Low, Freemont, CA (US);
Oscar Woo, Santa Cruz, CA (US);
Michael R. Fabry, Apple Valley, MN (US);
Terry A. Junge, Scotts Valley, CA (US);
Tiang Fee Yin, Singapore, SG;
Choon an Aw, Singapore, SG;
Jonathan E. Olson, Minneapolis, MN (US);
Chau Chin Low, Freemont, CA (US);
Oscar Woo, Santa Cruz, CA (US);
Michael R. Fabry, Apple Valley, MN (US);
Terry A. Junge, Scotts Valley, CA (US);
Tiang Fee Yin, Singapore, SG;
Choon An Aw, Singapore, SG;
Jonathan E. Olson, Minneapolis, MN (US);
Seagate Technology LLC, Scotts Valley, CA (US);
Abstract
Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.