The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2005
Filed:
Dec. 20, 2002
Manish Pandey, San Jose, CA (US);
Mitchell W. Hines, San Jose, CA (US);
Chih-chang Lin, San Jose, CA (US);
Manish Pandey, San Jose, CA (US);
Mitchell W. Hines, San Jose, CA (US);
Chih-Chang Lin, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
This invention relates to method and apparatus for verification of circuit designs containing memories. At a register transfer abstraction level, verification of a circuit design requires showing that the register transfer language (RTL) abstraction of the design is logically equivalent to the design implementation represented at the logic (e.g., gate and/or flip-flop) and/or the transistor (e.g. implementation verification) abstraction levels, as well as logic simulation of the design RTL embedded in a system-level test bench for verification at the system-abstraction level.