The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2005

Filed:

Nov. 24, 1999
Applicant:

Harsh Kumar, Fremont, CA (US);

Inventor:

Harsh Kumar, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1300 ; G11C 2900 ;
U.S. Cl.
CPC ...
Abstract

An error correction code apparatus has a processor located (on-chip) L2 tag and error correction and detection, and an off-chip L2 data array and second error correction and detection, the chips connected by a data bus. For a write operation, ECC bits are generated and transmitted with data to the off-chip array. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed. For a read operation, stored ECC bits and data are retrieved from the off-chip data array and transmitted to the core processor. New ECC bits are generated and compared to the original ECC bits. Correction is accomplished if needed.


Find Patent Forward Citations

Kumar, Harsh. (2005). Error correcting code scheme (U.S. Patent No. 6848070). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6848070

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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