The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6847122 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 25, 2005

Filed:

Oct. 16, 2003
Applicants:

Rakesh Batish, Royersford, PA (US);

C. Scott Kulicke, Fort Washington, PA (US);

Andrew Hmiel, Glenside, PA (US);

Walt Vonseggern, New Hope, PA (US);

Inventors:

Rakesh Batish, Royersford, PA (US);

C. Scott Kulicke, Fort Washington, PA (US);

Andrew Hmiel, Glenside, PA (US);

Walt VonSeggern, New Hope, PA (US);

Assignee:

Kulicke & Soffa Investments, Inc., Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2312 ; H01L 2348 ; H01L 2352 ; H01L 2940 ;
U.S. Cl.
CPC ...
Abstract

A method of packaging a semiconductor device including a plurality of elements is provided. The method includes applying an insulative material to at least a portion of the semiconductor device, where the insulative material includes insulative particles having a diameter smaller than a gap between adjacent conductors providing interconnection between the elements. The method also includes curing the insulative material.


Find Patent Forward Citations

Batish, Rakesh. (2005). System and method for preventing and alleviating short circuiting in a semiconductor device (U.S. Patent No. 6847122). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6847122

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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