The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2005
Filed:
Nov. 08, 2002
Mark A. Gerber, Austin, TX (US);
Bennett A. Joiner, Austin, TX (US);
Jose Antonio Montes DE Oca, New Braunfels, TX (US);
Trent A. Thompson, Austin, TX (US);
Mark A. Gerber, Austin, TX (US);
Bennett A. Joiner, Austin, TX (US);
Jose Antonio Montes De Oca, New Braunfels, TX (US);
Trent A. Thompson, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A package substrate () has a first surface, a second surface opposite a first surface, and a cavity () formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die () is placed in the cavity, and a conductive material () is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer () may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.