Wafer-level quasi-planarization and passivation for multi-height structures

Abstract

Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids. The methods are applicable to semiconductor device fabrication for electronic and photonic/optoelectronic systems such as, but not limited to, cell phones, networking systems, high brightness (HB) LEDs, laser diodes (LDs), photodiodes, modulator diodes and multifunction solar cells.