The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2005
Filed:
Jun. 24, 2003
Susan H. Downey, Austin, TX (US);
James W. Miller, Austin, TX (US);
Geoffrey B. Hall, Austin, TX (US);
Susan H. Downey, Austin, TX (US);
James W. Miller, Austin, TX (US);
Geoffrey B. Hall, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit () has a wire bond pad (). The wire bond pad () is formed on a passivation layer () over active circuitry () and/or electrical interconnect layers () of the integrated circuit (). The wire bond pad () is connected to a plurality of final metal layer portions (). The plurality of final metal layer portions () are formed in a final interconnect layer of the interconnect layers (). In one embodiment, the bond pad () is formed from aluminum and the final metal layer pads are formed from copper. The wire bond pad () allows routing of conductors in a final metal layer () directly underlying the bond pad (), thus allowing the surface area of the semiconductor die to be reduced.