The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2005
Filed:
Dec. 16, 2003
Geoffrey C-f Yeap, Austin, TX (US);
Srinivas Jallepalli, Austin, TX (US);
Yongjoo Jeon, Austin, TX (US);
James David Burnett, Austin, TX (US);
Rana P. Singh, Austin, TX (US);
Paul A. Grudowski, Austin, TX (US);
Geoffrey C-F Yeap, Austin, TX (US);
Srinivas Jallepalli, Austin, TX (US);
Yongjoo Jeon, Austin, TX (US);
James David Burnett, Austin, TX (US);
Rana P. Singh, Austin, TX (US);
Paul A. Grudowski, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.