The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2005

Filed:

Sep. 11, 2000
Applicants:

Yasuhiko Sasaki, Koganei, JP;

Kazuo Yano, Hino, JP;

Shunzo Yamashita, Tokorozawa, JP;

Koichi Seki, Hino, JP;

Inventors:

Yasuhiko Sasaki, Koganei, JP;

Kazuo Yano, Hino, JP;

Shunzo Yamashita, Tokorozawa, JP;

Koichi Seki, Hino, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06G 762 ; G06F 1750 ;
U.S. Cl.
CPC ...
Abstract

A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is 'no', e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).


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