The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
Mar. 24, 2003
Aaron Beverly, Los Gatos, CA (US);
Franco Carbognani, Calci, IT;
Shampa Gupta, San Jose, CA (US);
Prakash Parikh, Newark, CA (US);
Aaron Beverly, Los Gatos, CA (US);
Franco Carbognani, Calci, IT;
Shampa Gupta, San Jose, CA (US);
Prakash Parikh, Newark, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.