The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
Jun. 28, 2002
Conrad Dante, Portland, OR (US);
Conrad Dante, Portland, OR (US);
Lattice Semiconductor Corp., Hillsboro, OR (US);
Abstract
A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multiple programmable logic blocks that are configurable by a user. The logic blocks operate on data at a bit level resulting in unordered bits of information in a PLD domain. However, a vector processing block operates on data on a vector level (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). Thus, an interface is coupled between the programmable logic blocks and the vector processing block that converts at least a portion of the unordered bits of information from the PLD domain to one or more fixed-width vectors for use in the vector processing block. The interface may also perform scaling and/or sign extension on the unordered bits, to further free up expensive resources in the PLD domain.