Power layout structure of main bridge chip substrate and motherboard

Abstract

The present invention is a placement that is utilized in a 4 layers motherboard and a main bridge chip substrate. The layout adds a placement of the power rings and the power paths on the top signal layer and the bottom solder layer of the main bridge chip on the motherboard, the second layer and the third layer are planned as grounded layers, so that all signals on the top signal layer and the bottom solder layer on the motherboard can easily refer to the grounded layer. The layout of the power ring and the power path on the top signal layer on the motherboard is symmetrical to the layout of the power ring and the power path on the bottom solder layer on the motherboard, and all power paths couple to the corresponding power rings. The power bonding pads/solder balls are arranged on the area where the power rings and the power paths pass through, and the moderate quantity of the grounded bonding pads are arranged on the both sides of the power paths. Regarding to the layout of the main bridge chip substrate, the power of the graphics module, memory, subaltern bridge and APG are placed on the third layer and the bottom layer of the main bridge chip substrate. Moreover, more vias are provided to couple to the power paths.