The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 2005

Filed:

Oct. 31, 2001
Applicants:

Moon-hee Lee, Yongin, KR;

Woo-gwan Shim, Seoul, KR;

Hyung-ho Ko, Seoul, KR;

Jong-ho Chung, Seoul, KR;

Inventors:

Moon-hee Lee, Yongin, KR;

Woo-gwan Shim, Seoul, KR;

Hyung-ho Ko, Seoul, KR;

Jong-ho Chung, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 218242 ;
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device having a storage electrode of a capacitor is provided. The method includes the steps of: forming a contact hole perforating through an interlayer dielectric layer on a semiconductor substrate; forming a conductive plug to fill the contact hole and expose the surface of the interlayer dielectric layer; forming molds on the interlayer dielectric layer to expose the surface of the conductive plug; recessing the upper surface of the conductive plug to expose a portion of the sidewalls of the interlayer dielectric layer; forming an electrode layer to cover the recessed conductive plug, and the sidewalls of the interlayer dielectric layer and the molds; and removing upper surfaces of the electrode layer to make a storage electrode until molds are exposed. The method further includes the steps of: forming a conductive pad electrically connected to the semiconductor substrate and a lower insulating layer surrounding the conductive pad; and forming bit line stacks on the lower insulating layer, wherein the interlayer dielectric layer covers the bit line stacks, and the contact hole between the bit line stacks exposes the conductive pad.


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