The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 2005
Filed:
Aug. 22, 2003
Emrah Acar, Austin, TX (US);
Anirudh Devgan, Austin, TX (US);
Ying Liu, Austin, TX (US);
Sani R. Nassif, Austin, TX (US);
Haihua Su, Austin, TX (US);
Emrah Acar, Austin, TX (US);
Anirudh Devgan, Austin, TX (US);
Ying Liu, Austin, TX (US);
Sani R. Nassif, Austin, TX (US);
Haihua Su, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for determining full chip leakage power first estimates leakage power and dynamic power for each circuit macro. The power supply voltage to each macro is first assumed to be nominal. The power dissipation for each macro is modeled as a current source whose value is the estimated power divided by the nominal power supply voltage. The power distribution network is modeled as a resistive grids. The thermal environment of the IC and its electronic package are modeled as multi dimensional grids of thermal elements. Algebraic multi-grid (AMG) methods are used to calculate updated circuit macro voltages and temperatures. The macro voltages and temperatures are updated and updated leakage and dynamic power dissipation are calculated. Iterations are continued until leakage power converges to a final value.
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