The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2005

Filed:

Jan. 06, 2003
Applicants:

Kung-hong Lee, Ping-Tung Hsien, TW;

Ching-hsiang Hsu, Hsin-Chu, TW;

Ya-chin King, Tao-Yuan Hsien, TW;

Shih-jye Shen, Hsin-Chu, TW;

Ming-chou Ho, Hsin-Chu, TW;

Inventors:

Kung-Hong Lee, Ping-Tung Hsien, TW;

Ching-Hsiang Hsu, Hsin-Chu, TW;

Ya-Chin King, Tao-Yuan Hsien, TW;

Shih-Jye Shen, Hsin-Chu, TW;

Ming-Chou Ho, Hsin-Chu, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1604 ; H01L 29788 ;
U.S. Cl.
CPC ...
Abstract

An electrically erasable programmable logic device (EEPLD) contains a P-type substrate. A first N-type doped region is disposed in the P-type substrate. A first gate, which is used to store data, overlies the P-type substrate and is adjacent to the first N-type doped region. A second N-type doped region is laterally disposed in the P-type substrate. The second N-type doped region is also adjacent to the first gate. A second gate, which acts as a select gate or select gate of the EEPLD, overlies the P-type substrate and is adjacent to the second N-type doped region. A third N-type doped region is disposed in the P-type substrate. The third N-type doped region is adjacent to the second gate. By Applying a sufficient voltage on the first N-type doped region (V), and changing a select gate voltage (V) or the third N-type doped region voltage (V) applied on the second gate of the EEPLD, the operation of the EEPLD can be selectively implemented either under a channel hot hole (CHH) program mode or a channel hot electron (CHE) erase mode.


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