The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 2005

Filed:

Mar. 25, 2002
Applicants:

Yoshio Okayama, Ogaki, JP;

Keiichi Ueda, Gifu, JP;

Satoru Shimada, Gifu, JP;

Inventors:

Yoshio Okayama, Ogaki, JP;

Keiichi Ueda, Gifu, JP;

Satoru Shimada, Gifu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2176 ;
U.S. Cl.
CPC ...
Abstract

A method of fabricating a semiconductor device capable of remarkably reducing the quantity of misalignment after an etching step is obtained. This method of fabricating a semiconductor device comprises a first lithography step of transferring a mask pattern onto a first semiconductor substrate as a first resist pattern with positional reference to a first alignment mark, a first etching step of performing etching through the first resist pattern serving as a mask, a step of measuring the quantity of misalignment after the first etching step and a second lithography step of thereafter transferring the mask pattern onto a second semiconductor substrate as a second resist pattern while correcting the positional reference based on the first alignment mark on the basis of the quantity of misalignment after the first etching step. Thus, the positional reference in the second lithography step can be previously corrected to eliminate the quantity of misalignment after the etching step, whereby the quantity of misalignment after the second etching step is remarkably reduced.


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