The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2005

Filed:

Mar. 20, 2002
Applicants:

Billy Wayne Garrett, Jr., Mountain View, CA (US);

Frederick Abbott Ware, Los Altos Hills, CA (US);

Craig E. Hampel, San Jose, CA (US);

Richard M. Barth, Palo Alto, CA (US);

Don Stark, Los Altos, CA (US);

Abhijit Mukund Abhyankar, Sunnyvale, CA (US);

Catherine Yuhjung Chen, Milpitas, CA (US);

Thomas J. Sheffler, San Francisco, CA (US);

Ely K. Tsern, Los Altos, CA (US);

Steven Cameron Woo, Saratoga, CA (US);

Inventors:

Billy Wayne Garrett, Jr., Mountain View, CA (US);

Frederick Abbott Ware, Los Altos Hills, CA (US);

Craig E. Hampel, San Jose, CA (US);

Richard M. Barth, Palo Alto, CA (US);

Don Stark, Los Altos, CA (US);

Abhijit Mukund Abhyankar, Sunnyvale, CA (US);

Catherine Yuhjung Chen, Milpitas, CA (US);

Thomas J. Sheffler, San Francisco, CA (US);

Ely K. Tsern, Los Altos, CA (US);

Steven Cameron Woo, Saratoga, CA (US);

Assignee:

Rambus Inc., Los Altos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1340 ;
U.S. Cl.
CPC ...
Abstract

A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.


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