The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2005

Filed:

Apr. 02, 2001
Applicants:

David Michael Rogers, Sunnyvale, CA (US);

Mimi Xuefeng Qian, Campbell, CA (US);

Roger Huazne Tsao, San Jose, CA (US);

Michael Allen Van Buskirk, Saratoga, CA (US);

Inventors:

David Michael Rogers, Sunnyvale, CA (US);

Mimi Xuefeng Qian, Campbell, CA (US);

Roger Huazne Tsao, San Jose, CA (US);

Michael Allen Van Buskirk, Saratoga, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3126 ; G01R 3108 ; H01L 2358 ;
U.S. Cl.
CPC ...
Abstract

A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a dummy device, a fourth transistor is coupled to the dummy device and to the third transistor. The transistors are of a common type. The characterization method further includes applying non-overlapping clocking signals to transistors of the test circuit to produce test signals for application to the device under test and detecting a current in one or more transistors from the device under test. The bias voltage is further varied to characterize the device under test.


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