The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2005

Filed:

Aug. 27, 2003
Applicant:

Motoshige Igarashi, Tokyo, JP;

Inventor:

Motoshige Igarashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27088 ;
U.S. Cl.
CPC ...
Abstract

Gate electrodes () are formed on a semiconductor substrate (), each with a gate insulating film () interposed therebetween. A pair of offset spacers () are respectively formed on opposite side faces of each of the gate insulating film () and the gate electrodes (). Diffusion layers () are formed in the semiconductor substrate () on opposite sides of a portion of the semiconductor substrate () immediately under each of the gate electrodes (), by ion implantation. While the gate electrodes () have various configurations such as a gate electrode having a rectangular section, an upwardly tapered gate electrode and a downwardly tapered gate electrode, respective configurations of the offset spacers () are adjusted so that lengths each obtained by adding the gate length of the gate electrode (), which gate length extends on an interface between the gate insulating film () and the gate electrode (), to a width of the pair of the offset spacers (), which width extends on an interface between the offset spacers () and the semiconductor substrate (), are substantially uniform.


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