The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
Jul. 12, 1999
Tushar R. Gheewala, Los Altos, CA (US);
Michael J. Colwell, Fremont, CA (US);
Henry H. Yang, San Jose, CA (US);
Duane G. Breid, Lakeville, MN (US);
Tushar R. Gheewala, Los Altos, CA (US);
Michael J. Colwell, Fremont, CA (US);
Henry H. Yang, San Jose, CA (US);
Duane G. Breid, Lakeville, MN (US);
Virage Logic Corporation, Fremont, CA (US);
Abstract
A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell design with smaller, single-height cells for high-density applications. The single-height cells may be used where possible and higher-drive dual-height basic cells where larger transistors are desired. Other multiple height cells may also be included if even more current is desirable. The power rail may include conductors of varying width.