The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
Jan. 13, 2003
Robert J. Gauthier, Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Xiaowei Tian, Essex Junction, VT (US);
Minh H. Tong, Essex Junction, VT (US);
Steven H. Voldman, South Burlington, VT (US);
Robert J. Gauthier, Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Xiaowei Tian, Essex Junction, VT (US);
Minh H. Tong, Essex Junction, VT (US);
Steven H. Voldman, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a normal MOSFET but extends deeper into the silicon since the present invention uses a resistor well as the source/drain. The deeper emitter/collector increases the second trigger current of the NFET when used as an ESD protection device.