The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 2005
Filed:
May. 01, 2003
Daniel T. Pham, Austin, TX (US);
Alexander L. Barr, Austin, TX (US);
Leo Mathew, Austin, TX (US);
Bich-yen Nguyen, Austin, TX (US);
Anne M. Vandooren, Austin, TX (US);
Ted R. White, Austin, TX (US);
Daniel T. Pham, Austin, TX (US);
Alexander L. Barr, Austin, TX (US);
Leo Mathew, Austin, TX (US);
Bich-Yen Nguyen, Austin, TX (US);
Anne M. Vandooren, Austin, TX (US);
Ted R. White, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method for forming a polysilicon FinFET () or other thin film transistor structure includes forming an insulative layer () over a semiconductor substrate (). An amorphous silicon layer () forms over the insulative layer (). A silicon germanium seed layer () forms in association with the amorphous silicon layer () for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (). During the annealing step, silicon germanium seed layer (), together with silicon germanium layer (), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (), drain (), and channel () regions are formed within the polysilicon layer. A double-gated region () forms in association with source (), drain (), and channel () to produce polysilicon FinFET ().