The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 2005

Filed:

Sep. 26, 2003
Applicants:

Mitsuru Kaneda, Tokyo, JP;

Hideki Takahashi, Tokyo, JP;

Inventors:

Mitsuru Kaneda, Tokyo, JP;

Hideki Takahashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21332 ; H01L 2974 ;
U.S. Cl.
CPC ...
Abstract

An N-type silicon substrate () has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N-type silicon substrate (), a P-type impurity diffusion layer () of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N-type silicon substrate (), a P-type isolation region () is partially formed by diffusing a P-type impurity. The P-type isolation region () has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (). As viewed from the upper surface side of the N-type silicon substrate (), the P-type isolation region () is formed, surrounding an Nregion () which is part of the N-type silicon substrate (). The Nregion () surrounded by the P-type isolation region () is defined as an element formation region of the N-type silicon substrate (). Thus obtained are a semiconductor device and a method of manufacturing the same, and a semiconductor substrate and a method of manufacturing the same, which make it possible to retain bidirectional breakdown voltages and ensure high reliability.


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