The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 2004
Filed:
Mar. 07, 2001
Yasunori Chikawa, Kitakatsuragi-gun, JP;
Hiroaki Kitazaki, Soraku-gun, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A re-wiring layer is provided on a circuit-formed surface of an IC chip, in an area other than where external lead electrodes. In the process for forming a circuit of the IC chip, the re-wiring layer is formed in a step following to a circuit forming step, and the rewiring layer formation is executed as a part of the IC chip fabrication process. The re-wiring layer is provided with first electrode pads on a chip periphery, second electrode pads at positions closer to the IC chip than the positions of the first electrode pads, and wires or traces for connecting the first electrode pads with the second electrode pads according to the 1:1 correspondence therebetween. By so doing, it is possible to provide a semiconductor device that allows the number of possible combinations of sizes of the laminated semiconductor chips to increase, while ensuring that an increase in the package cost, an increase in the thickness of the package, and deterioration of the package production efficiency can be suppressed.