The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 2004

Filed:

Jul. 14, 2003
Applicant:
Inventors:

Jeff P. Erhardt, San Jose, CA (US);

Hiroyuki Kinoshita, Sunnyvale, CA (US);

Cyrus Tabery, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ; H01L 2/14763 ; H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1302 ; H01L 2/14763 ; H01L 2/1336 ;
Abstract

The invention is an apparatus and a method of manufacturing a structure. The method includes the step of patterning a layer to include a line and space pattern. A space of the line and space pattern in a first region includes a first critical dimension less than achievable at a resolution limit of lithography. A line of the line and space pattern in a second region includes a second critical dimension achievable at a resolution limit of lithography. A sidewall spacer is formed on a line from a masking layer used in the formation of the structure. The method uses one critical masking step and two non-critical masking steps.


Find Patent Forward Citations

Quick Actions:

Erhardt, Jeff. (2004). Partially de-coupled core and periphery gate module process (U.S. Patent No. 6835662). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6835662

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…